A conventional integrated circuit (IC) may include millions of logic gates. The logic gates must be fabricated properly in order for the IC to operate as designed. Testing techniques have therefore developed to ensure that the logic gates of an IC have been properly fabricated and provide proper functioning to the IC.
According to some testing techniques, automatic test equipment (ATE) transmits test data to input pins of an IC, receives output from the IC, and determines whether the logic gates of the IC are functioning properly based on the output. The I/O speed and storage capacity of such test equipment is not suitable for use in conjunction with many modern ICs, including microprocessors and application-specific ICs. For example, the amount of test data needed to provide adequate fault coverage for modern ICs often exceeds ATE storage capacity. Additional storage capacity may be obtained by purchasing memory expansion modules or more advanced ATE, but this approach is often cost-prohibitive.
Even if ATE storage capacity is suitable for given test data, slow ATE I/O speeds result in long test times that increase as the amount of test data increases. The test speed is limited to the ATE I/O speed even if (as is usually the case) an IC under test is capable of processing the test data at much higher speeds. The long test times limit the number of ICs that can be tested in a given period and thereby limit IC production throughput.
The above problems may be addressed by limiting amounts of test data used to test an IC. Such an approach results in less effective testing and is usually unacceptable. Built-In Self Test (BIST) is another approach in which test data for an IC is embedded in test sequences generated by BIST hardware located on the IC.
FIG. 1 illustrates a common BIST architecture known as STUMPS (Self-Testing Using MISR [Multiple Input Signature Register] and Parallel SRSG [Shift Register Sequence Generator]). Architecture 1 includes Parallel Random Pattern Generator (PRPG) 2 and phase shifter 3 for generating pseudo-random test patterns. During a test, these test patterns are shifted into scan chains 4 through 7 of the IC in which architecture 1 is implemented. Outputs of scan chains 4 through 7 are received by XOR tree 8, which generates a test signature based on the outputs. MISR 9 receives the test signature and determines if the test was successful based thereon.
Although the conventional BIST approach reduces ATE storage and I/O constraints, conventional BIST is impractical due to signal constraints imposed by some IC designs. Moreover, BIST requires a large amount of test data in order to obtain adequate fault coverage. These drawbacks may be alleviated by weighting the pseudo-random test patterns based on the scan chains to which they will be applied. Weights appropriate for a particular scan chain may be determined using Automatic Test Pattern Generation (ATPG) techniques, but current BIST-based approaches are unable to satisfactorily store and apply the required weights. This deficiency is particularly pronounced in cases where a test pattern developed using ATPG requires specific bit values at specific positions in the test pattern.
Current encoding schemes are sometimes used to compress test data for ATE storage. The compressed data may be decompressed on an IC under test and shifted through its functional logic at a speed greater than the ATE I/O speed, thereby reducing required test time. One class of encoding schemes is referred to as run-length encoding. According to run-length encoding, a run consists of consecutive occurrences of a particular symbol or data value. A length of a run is equal to the number of consecutive occurrences.
Runs may be converted into code words according to the tables shown in FIGS. 2 and 3. As shown in the FIGS., each run corresponds to a prefix and a suffix that are concatenated to create a code word associated with the run. The prefix identifies the “bucket” to which the run belongs, and the suffix identifies the run within the identified bucket.
Table 10 of FIG. 2 represents a conventional Goulomb encoding scheme. Goulomb encoding uses a variable-length prefix followed by a fixed-length suffix. Each prefix identifies a bucket that includes 2suffix—length runs. In FIG. 3, table 20 illustrates another run-length encoding scheme. This scheme also uses a variable-length prefix to identify a bucket of runs, but the length of a suffix corresponding to a bucket is identical to the length of the prefix that identifies the bucket. In the table 20 scheme, each prefix of length k identifies a bucket that includes 2k runs. For certain types of data, these conventional encoding schemes produce unsatisfactory compression ratios. Moreover, these schemes cannot be used to encode and decode certain types of data.